FIG. 10 shows a typical configuration of an address decoder circuit of a related technique. In a synchronous memory, a word line signal is converted to a pulsed signal for control. In the example of FIG. 10, four bit address signals AD[0] to AD[3] are decoded to 16 bit word line signals WL[0] to WL[15]. The address signals are decoded on the two-bit basis into four bit selection signals XA1[3:0] and XA2[3:0] and, as AND logic is taken between a reference clock signal CLK0 that determines the pulse width of a word line signal WL, and the signals XA1 [3:0], XA2 [3:0], finally word line signals WL are generated.
To implement the AND logic, a static CMOS NAND gate and an inverter gate are generally used. The transistor ratio of the CMOS gate is determined so that the pulse width will be set at a constant value until the clock signal CLK gets to the signal WL.
In the case of an inverter gate, for example, the ratio of the gate width of a PMOS transistor and that of an NMOS transistor is set to approximately 2:1 and, in the case of a NAND gate, the ratio of the gate width of the PMOS transistor and that of the NMOS transistor is set to 1:1. It is observed that, if a static CMOS gate is used, there is set a limit to increasing the operating speed of the address decoder.
When a pulse signal is propagated through a static CMOS gate, there occurs first the signal propagation for activation, followed by the signal propagation for deactivation. A critical path is a signal propagation path for activation.
A pulse generation circuit used for increasing the operating speed of the CMOS gate, through which a pulse signal is propagated, is disclosed in Patent Document 1 (JP Patent Kokai JP-A-2004-32151). The pulse generation circuit includes:
a gate having a first output transistor that sets an activation level and a second output transistor that sets a deactivation level,
a first inverter string made up of a plurality of inverters connected in cascade to propagate a set pulse SET to drive a first output transistor,
a second inverter string made up of a plurality of inverters connected in cascade to propagate a reset pulse RESET that controls the deactivation of the output pulse to drive a second output transistor, and
a reset transistor provided at an inverter output of the first inverter string. The reset transistor drives a pulse edge of the inverter output corresponding to a trailing edge of the set pulse SET in response to the reset pulse RESET propagated through the second inverter string to prevent delay of a pulse edge corresponding to a trailing side edge of the set pulse SET. With this pulse generating circuit, the part of the transistors that propagate the signal for deactivation is disconnected from the path of propagation of the pulse signal to lower the gate input capacitance to allow for faster propagation of the signal for activation. On the other hand, if the transistor parts are simply disconnected, the signal for deactivation is propagated at a lower speed. Thus, to control the disconnected transistor parts, there are newly provided a signal path for propagating the signal for deactivation using an inverter string and a reset signal RS propagated through the inverter string.
A signal RS has a constant pulse width and rises simultaneously as the falling of the clock signal CLK. This prevents the signal for deactivation from being propagated at a lower speed.
FIG. 11 shows a configuration of an address decoder circuit 410 to which this speed-raising technique has been applied. A signal RS0 for deactivation is newly provided and propagated using an inverter string. In an AND circuit 200 that forms an address decoder circuit 200, a transistor for propagating a signal for deactivation is replaced by two transistors.
The divided transistors are a PMOS transistor for a NAND gate and an NMOS transistor for an inverter gate. The PMOS transistor has a source connected to a power supply, a drain connected to CLKB and a gate connected to RSB. The NMOS transistor has a drain connected to CLK1, a source connected to GND and a gate connected to RS.
One of the two transistors is controlled by a reset signal propagated through the inverter string. This should achieve the high-speed operation of the address decoder circuit.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2004-32151A